Modern circuit simulations or verifications often encounter circuit models having a large number of inter-connected circuit elements. For example, during the final timing verification of Integrated circuits (IC), the number of parasitic resistors and capacitors in the circuit model may reach or exceed 107. In order to improve the efficiency of circuit analysis, a variety of RC reduction technologies have been developed during the last decade.
The dominant trend in RC reduction has been towards transforming the original RC circuit network into a mathematical macro-model so that certain mathematical techniques can be utilized to generate a reduced mathematical circuit model. (See Rohrer et. al., “Asymptotic Waveform Evaluation for Timing Analysis”, IEEE Trans. Computer Aided Design, vol. 9, pp. 352–66, 1990.) Such transformations also preserve the electrical properties of each input and output port. A disadvantage of these transformations, however, is that the reduced circuit model is not realizable. In other words, the reduced mathematical circuit model contains higher order elements that can not be realized as RC circuits. A drawback associated with this unrealizability is that the resulting mathematical models may presume special, often non-standard simulator capabilities.
Liao et al. in “Partitioning and Reduction of RC Interconnect Networks Based on Scattering Parameter Macromodels”, ICCAD 1995, pp. 704–09 (hereinafter “Liao”) presented a realizable reduction scheme in which the original circuit model was partitioned into several sub-circuits. Each sub-circuit was then synthesized to produce a reduced sub-network that approximates the original sub-circuit. A weakness of the approach in Liao is that the reduction scheme may not be effective for circuits containing certain types of circuit topologies, such as coupling capacitors or an unbalanced tree in a memory block. Moreover, there is no guarantee that errors resulted from the approximations are controlled to a minimized or negligible level so that certain properties of the original circuit are preserved.
Sheehan in “TICER: Realizable Reduction of Extracted RC Circuits”, ICCAD 1999 (hereinafter “TICER”) proposed a method of achieving realizable reduction of RC circuit with certain controlled accuracy in the neighborhood of an eliminated node. Details of Sheehan's method can be found in TICER, the content of which is incorporated hereby in its entirety as reference. Sheehan's method is based on node elimination. According to Sheehan, a node can be a quick, slow, or normal node depending on its time constant. The time constant of a node N is the total capacitance (χN) from the node to other nodes and to ground divided by the sum of conductance (γN) from the node to other nodes and to ground. Each node of a circuit is classified as a quick, slow, or normal node according to whether its time constant is less than, greater than, or between the minimum and maximum time constants defining the frequency range of interest. Sheehan concluded that quick nodes can be eliminated from the circuit network without significantly altering its behavior (such as delay characteristics or more specifically the Elmore delay) in the frequency range of interest.
Sheehan then presented a time constant equilibration reduction (TICER) algorithm that reduces an RC circuit by successively finding quick nodes in the circuit and then eliminating them by the following procedures. To eliminate a quick node N, first remove all resistors and capacitors connecting other nodes to node N. Then insert new resistors and capacitors between former neighbors of node N according to the following two rules. If node i and node j had been connected to node N through conductance giN and gjN, insert a conductance giNgjN/γN between nodes i and j. If node i had a capacitor CiN connected to node N and node j had a conductance gjN connected to node N, insert a capacitor CiNgjN/γN between nodes i and j. A drawback of the TICER algorithm is that it only focuses on controlling the accuracy of circuit simulation and ignores the topological impact of node eliminations. This is because although TICER reduces the number of nodes, it may increase the number of resistors or capacitors between nodes neighboring the eliminated nodes. The increased number of resistors or capacitors could further complicate the entanglement between the remaining nodes. To further illustrate TICER's drawback, consider an example shown in FIG. 1. FIG. 1 shows a circuit fragment (or a “regional” circuit topology) comprising a quick node N having four neighboring nodes 1–4 connected to node N through four resistors with conductance g1N . . . g4N. Eliminating node N according to TICER produces six new conductance connected between the four neighboring nodes. In general, eliminating a quick (or slow) node having M neighboring nodes could produce M(M−1)/2 new resistors or capacitors between the neighboring nodes. These new resistors or capacitors could further aggravate the subsequent circuit analysis. As a result, TICER may not achieve significant circuit reduction for large circuit networks
There is therefore a need to provide a method of producing a reduced topology that takes into account both the physical and topological characteristics of the circuit network. There is also a need to provide a system that implements the above method.